There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Semiconductor-on-insulator (SOI) is a material which may be used to fabricate such integrated circuits. Such integrated circuits are known as SOI devices and may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET devices.
One example of an SOI device is a semiconductor dynamic random access memory (“DRAM”) device. Such a semiconductor DRAM device may include an electrically floating body in which electrical charges may be stored. The electrical charges stored in the electrically floating body may represent a logic high or binary “1” data state or a logic low or binary “0” data state.
Various techniques may be employed to read data from and/or write data to a semiconductor DRAM device having an electrically floating body. In one conventional technique, a memory cell having a memory transistor may be read by applying a bias to a drain region of the memory transistor, as well as a bias to a gate of the memory transistor that is above a threshold voltage of the memory transistor. As such, conventional reading techniques may sense an amount of channel current provided/generated in response to the application of the bias to the gate of the memory transistor to determine a state of the memory cell. For example, an electrically floating body region of the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: binary “0” data state and binary “1” data state).
Also, conventional writing techniques for memory cells having an N-Channel type memory transistor typically result in an excess of majority charge carriers by channel impact ionization or by band-to-band tunneling (gate-induced drain leakage “GIDL”). The majority charge carriers may be removed via drain side hole removal, source side hole removal, or drain and source hole removal, for example, using back gate pulsing.
Often, conventional reading and writing techniques may lead to relatively large power consumption and large voltage drivers which occupy large amount of area on a circuit board or die and cause disruptions to memory cells on unselected rows of an array of memory cells. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of charge carriers in an electrically floating body region of a memory cell in a semiconductor DRAM device, which, in turn, may gradually reduce, and even eliminate a net charge representing data stored in the memory cell. In the event that a negative voltage is applied to a gate of a memory cell transistor, thereby causing a negative gate bias, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate, and a net charge associated with majority charge carriers located in the electrically floating body region may decrease over time. This phenomenon may be characterized as charge pumping, which is a problem because the net quantity of charge carriers may be reduced in an electrically floating body region of the memory cell, which, in turn, may gradually reduce, and even eliminate, a net charge representing data stored in the memory cell.
In view of the foregoing, it may be understood that there are significant problems and shortcomings associated with reading from and/or writing to electrically floating body semiconductor dynamic random access memory (“DRAM”) devices using conventional reading/writing techniques.